1. Field of the Present Invention
The present invention relates to a method of forming a floating gate and to a method of manufacturing a non-volatile semiconductor memory device comprising a floating gate.
2. Description of the Related Art
Semiconductor memory devices are generally divided into volatile semiconductor memory devices and non-volatile semiconductor memory devices. In the volatile semiconductor memory device, data stored in the cell is dissipated when power is not applied. However, in the non-volatile semiconductor memory, stored data in the cell is retained even when power is not applied thereto. Because non-volatile semiconductor memory devices can store data for long periods of time, they are used to meet the current high demand for flash semiconductor memory devices such as EEPROMs (Electrically Erasable and Programmable Read Only Memories).
Meanwhile, flash semiconductor memory devices can be generally categorized as stacked flash semiconductor memory devices and spilt gate flash semiconductor memory devices. The split gate type of flash semiconductor memory device has a structure wherein a floating gate and a control gate are separated from each other, and the floating gate is electrically insulated from the outside. Information is stored in a memory cell of the split gate type of flash semiconductor memory device using the principle that current in a memory cell changes depending on electron injection (programming)/electron discharge (erasing) into/from the floating gate. In the electron injection, hot electrons are injected into the floating gate by a channel hot electron injection (CHEI) mechanism. The electron discharge is accomplished by Fowler-Nordheim (F-N) tunneling through a tunnel insulation layer between the floating gate and the control gate of the split gate type of flash semiconductor memory device. In connection with the electron injection (programming) and electron discharge (erasing), a voltage distribution may be explained as an equivalent capacitor model. Recently, the split gate type of flash semiconductor memory device has been widely used for the purpose of storing data.
The efficiency of the split gate type of flash semiconductor memory device required depends on the ease in which electrons can be transferred from the floating gate to the control gate. Therefore, various research into the structure of the floating gate aims at improving the efficiency of electron transference in the hope of realizing a floating gate having a small cell and, in turn, a non-volatile semiconductor memory device having lower power consumption, and an excellent ability to be integrated with a logic device.
For example, U.S. Pat. No. 5,029,130 discloses a method of manufacturing a floating gate capable of promoting the transference of electrons from the floating gate to a control gate. The method entails oxidizing an upper portion of the floating gate to increase the sharpness of the edge of the floating gate. However, the sharpness is increased only at the upper portion of the floating gate. Accordingly, the speed at which electrons can be transferred from the floating gate to the control gate is still rather limited.
Korean Laid-Open Patent Publication No. 2001-91532 discloses a method of manufacturing a split gate type of flash semiconductor memory device in which a gate oxide is formed on a silicon substrate, and then a polysilicon layer and a nitride layer are sequentially formed on the substrate including over the gate oxide. The nitride layer is selectively etched by a photolithographic process to form a nitride mask pattern. Then, an oxide layer is formed on the polysilicon layer. The polysilicon layer and the nitride mask pattern are removed by etching to leave a portion of the polysilicon layer beneath the oxide layer. After an interpoly tunnel insulation layer is formed, a control gate is formed on the oxide layer, the interpoly tunnel insulation layer and the gate oxide. Impurities are implanted between the polysilicon layer and the oxide layer to form source/drain regions, whereby the split gate type flash semiconductor memory device is completed. According to the above-mentioned publication, the split gate flash semiconductor memory device has enhanced programming and erasing efficiencies and improved endurance in terms of its programmability and erasability.
Meanwhile, Japanese Laid-Open Patent Publication No. 1999-26616 discloses a split gate type of memory device including an insulation layer for a floating gate formed on a semiconductor substrate, an insulation layer on the floating gate, a sidewall silicon oxide layer covering the sidewall of the floating gate, and a control gate insulated from the floating gate by the insulation layer and the sidewall silicon oxide layer. In this split gate type of memory device, the floating gate comprises polysilicon, and a silicon oxide layer is substituted for at least a portion of the polysilicon near the sidewall of the floating gate electrode. According to the publication, data writing and holding characteristics of the split gate type of memory device are improved without causing variations in the threshold voltage at the control gate, and data from being excessively erased.
However, in the methods described above, additional processes are required for forming the insulation layer between the floating gate and the control gate, and the gates may not be precisely aligned. Therefore, problems still remain, such as excessive cell size and the difficulty of integrating the memory device with a logic device.